• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The faceplate of a square-planar picture tube is relatively flat, with a curvature along the major axis and lines parallel thereto that is generally greater near the left and right edges than in the center. An LC tuned circuit, coupled to the deflection winding, has a resonant period of oscillation approximately half that of the line trace interval. The tuned circuit introduces an oscillatory correction component into the trace current that provides additional S-shaping in that portion of the line scan intermediate the center and the left or right edge.
    公开号:SU1736352A3
    申请号:SU853990802
    申请日:1985-12-03
    公开日:1992-05-23
    发明作者:Эдвард Хаферл Петер
    申请人:Рка Корпорейшн (Фирма)；
    IPC主号:
    专利说明:

    The invention relates to television, specifically to deflection voltage correction devices.
    The purpose of the invention is to improve the accuracy of the formation of the correction signal.
    Fig. 1 is an electrical schematic diagram of a device for generating a correction signal in a horizontal scanning output stage; Fig. 2 illustrates stress plots.
    The device for generating a correction signal in the horizontal output stage includes a switch 1, a damping diode 2, a reverse capacitor 3, a horizontal deflecting system 4, an S-forming capacitor 5, an inductor 6, an additional capacitor 7.
    A device for generating a correction signal in a horizontal scanning output stage operates as follows.
    The horizontal synchronizing signal (Fig. 2, a) is supplied to the sweep switch 1 to form a sweep current component (Fig. 2, b) and deflecting along the line during the forward running interval between the times ti and ta and the reverse current component sweep on the reverse interval between the moments t and IB. When the sweep switch 1 is non-conductive on the flyback interval, the flyback voltage pulse Vi (Fig. 2a) is created on the flyback capacitor 3. The energy stored in the input choke, connected between the B + terminal and the sweep switch 1, compensates for the loss of the horizontal deviation.
    The sweep current in the horizontal deflection system 4 is a sawtooth current. S-forming; capacitor 5 and horizontal deflection calculator, ia 4, form the first resonant circuit, which resonates at a certain frequency, which is less than the horizontal scanning frequency fcrp 15625 kg.
    The shape of the current (Fig. 2, b) is obtained when only the S-forming capacitor 5 is used for S-correction, the slope di / dt of the diverting current determines the distance between the displayed video signal lines. When using only S-shaped capacitors 5, incomplete correction S is carried out with a current of 1 cm (Fig. 2, b). The di / dt slope of the dotted current AND curve and in the intermediate areas to the left and right of the central part is large, which leads to image expansion in these areas in comparison with the image in the other areas.
    Coil 6 inductance and additional capacitor 7, forming the second resonant circuit, create an additional S-correction to create
    The S-corrected form of the deflecting current i, shown in FIG. 2, b, is additionally corrected at all points along the horizontal scanning.
    Using a (adjustable) coil 6
    The inductance of the second resonance circuit is adjusted so that the period of resonant oscillations is half the duration of the forward sweep stroke. This gives two cycles of oscillation current 2 on additional
    the capacitor 7 on the interval duration of the forward stroke sweep. As can be seen from Fig. 2c, the oscillation of current 2 is symmetrical about the middle of the forward stroke duration, i.e. moment t4.
    During the reverse stroke, the first resonant circuit, consisting of a reverse capacitor 3 and a horizontal deflection system 4, triggers an S-forming capacitor 5 and an inductor 6 with current
    reverse sweep, creating approximately one cycle of current oscillation 2 for the duration of the reverse stroke, between the instants of time ty and is (figure 2, c). Correct phasing of two current cycles
    the oscillation during the forward stroke and one cycle of the current oscillation during the reverse stroke is due to the fact that current 2 becomes approximately zero at the beginning and at the end of the duration interval
    the forward stroke, respectively, at times ti and t (see Fig. 2, d). To ensure that the correction is symmetric about the midpoint of the forward stroke, it is desirable that current 2 be in the same phase as in
    the beginning of the forward stroke at times to and ti in figure 2, in, and at the end of the forward stroke, at times to and t2.
    The amplitude of the current 2 is determined by the value of the inductor 6.
    Phase, frequency, and amplitude of current 2 are corded with an S-capacitor Cs, to co-generate a resultant deflecting current of the form and (FIG. 2, c) having the required form for correcting the geometric nonlinearities of the horizontal scan of the quadratic-planar kinescope. Voltage VL.H. attached to the deflecting winding LH during the forward stroke, is the sum of the S-capacitor voltage VGS and the voltage V2 between the terminals 2 and 1 of the inductor 6 Therefore h V2. Voltage V2, shown in Fig. 2, g, delays current 2 by 90 ° during forward travel and, therefore, is proportional to di / dt. Thus, VLH LH, di / dt Vcs + Kdi2 / dt, where K is a constant value.
    From the above, it can be noted that the component voltage S of the capacitor in the voltage applied to the deflecting winding LH introduces a current component during the forward stroke, similar in profile to the current shown by the dashed line (see Fig. 2, d) tuned circuit 60 introduces component V2 applied to the deflection winding, which is proportional to di / dt.
    When the current 2 (FIG. 2, c) drops linearly, for example, from the time p and t2, from the time t4 and ts and from the time te to ty, the current g creates an increment of the slope of the deflecting current t, beyond that which introduces indicated by the dotted line component of the current of the S-capacitor ii. At these intervals, the image is expanded.
    When the current 2 (FIG. 2, c) increases linearly in the left and right from the center of the horizontal scanning regions from t2 to ta and from ts and ta, di / dt, or the inclination of the current i2 is opposite to di / dt, the dashed line component of the S-capacitor current, and in these areas, the slope of the deflecting current and decreases, creating an image compression.
    Figure 2, d shows the current 1h flowing through the inductor. The flat parts of the current indicate an increased slope di / dt of the deflecting current i. Steep areas indicate a decrease in di / dt.
    The high quality factor of circuit 60 is preferred to provide symmetric S-correction.
    By selecting the nominal S-capacitor so as to ensure a slight overcorrection or compression of the image in the middle and on the left and right edge of the line scan and so that a slight undercorrection or expansion in the
    left and right from the middle of the regions, it is possible to achieve that the resonant circuit 60 will introduce a compensating correction current component i2, which counteracts the pair and undercorrection,
    performed by a capacitor Cs, substantially linearized the image along the entire horizontal scan.
    权利要求:
    Claims (1)
    [1]
    Invention Formula
    A device for generating a correction signal in the horizontal output stage, comprising a switch configured on a transistor, the base of which is an input to the scanning signal, a damping diode and a return capacitor connected in parallel between the collector and the emitter of the transistor, with the emitter output of the transistor connected to the common bus and the collector output of the transistor is connected to the first output of the horizontal deflection system via an S-forming capacitor, the second output of the horizontal deflection systems coupled to a terminal of the inductor of Whitlock ichayuschees in that, in order to increase the accuracy of forming the correction signal, introduced an additional capacitor, a first terminal of which is connected to the first terminal of the inductor,
    the second terminal of which is connected to the common bus, and the inductor and the capacitor form an oscillating circuit tuned to a frequency having a period equal to half the period
    sweep frequency.
    /
    6
    52 8Ms-jll sf
    Phage. 2
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US2817788A|1954-11-18|1957-12-24|Rca Corp|Television deflection system circuitry|
    US2916665A|1955-10-24|1959-12-08|Motorola Inc|Sawtooth current generator|
    US3428853A|1964-04-04|1969-02-18|Hitachi Ltd|Electron beam deflection device for use in connection with cathode-ray tubes of television receivers and the like|
    NL6407634A|1964-07-04|1966-01-05|
    GB1309997A|1970-10-31|1973-03-14|Fernseh Gmbh|Deflection circuit|
    JPS5312220A|1976-07-21|1978-02-03|Hitachi Ltd|Non-linearlity correction unit for horizontal deflection circuit|
    US4181874A|1977-12-12|1980-01-01|Rca Corporation|Television S-correction circuit with improved linearity|
    US4176303A|1978-05-17|1979-11-27|Rca Corporation|Television S-correction linearity device|
    JPS5645248U|1979-09-18|1981-04-23|GB8506107D0|1985-03-08|1985-04-11|Rca Corp|East-west vertical parabola shaper|
    DE3619279A1|1986-06-11|1987-12-17|Thomson Brandt Gmbh|CIRCUIT ARRANGEMENT FOR ELIMINATING GEOMETRY DISTORTIONS|
    US5508593A|1994-05-11|1996-04-16|Thomson Consumer Electronics, Inc.|Differential error convergence correction|
    DE69517747T2|1994-05-11|2000-11-09|Thomson Consumer Electronics|Circuit for correcting convergence|
    US5847777A|1994-05-11|1998-12-08|George; John Barrett|Right-edge differential error convergence correction|
    JP3137574B2|1995-11-21|2001-02-26|松下電子工業株式会社|Image distortion correction device|
    FR2775549B1|1998-02-27|2000-03-31|Thomson Multimedia Sa|IMAGE DEFORMATION CORRECTION METHOD AND DEVICE USING THE SAME|
    US6586895B2|2001-05-08|2003-07-01|Thomson Licensing S.A.|Raster distortion correction circuit|
    JP5375521B2|2009-10-27|2013-12-25|ソニー株式会社|High frequency amplifier and wireless communication device|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    GB848408694A|GB8408694D0|1984-04-04|1984-04-04|Dynamic "s" correction|
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